1. Field of the Invention
The present invention relates to a level shifter circuit which generates an output signal having a desired level in response to the level of an input signal and more particularly to a level shifter circuit effectively employed in a semiconductor device or the like.
2. Description of Related Art
FIG. 2 is a circuit diagram illustrating a conventional level shifter circuit which converts the voltage level of the potential difference between the first power source voltage Vcc and an input signal .phi.1, input from an input terminal 1, having an amplitude of the ground voltage Vss, into the voltage level of an output signal .phi.2, output from an output terminal 2 to a second stage circuit, having an amplitude of the potential difference between the second power source voltage Vpp higher than the first power source voltage Vcc and the ground voltage Vss.
The level shifter circuit shown in FIG. 2 incorporates therein an inverter 3 which inputs the input signal .phi.1 and an inverter 4 which inputs the output of the inverter 3 through a node N3 and outputs an inverted signal of the output from the inverter 3. The level shifter circuit also incorporates P channel type field effect transistors (hereinafter referred as PMOS) 5 and 6, in which the power source voltage Vpp is applied to each source and each drain is cross-connected to the other each gate, and N channel type field effect transistors (hereinafter referred as NMOS) 7 and 8 which are respectively connected between the drains of each PMOS 5 and PMOS 6 and the ground Vss and turn on and off in accordance with a potential level of a node N3 or a node N4 input to each gate. The drain of NMOS 7 is connected, at a node N5, to the drain of PMOS 5, and PMOS 6 turns on and off in response to the potential of the node N5. The drain of NMOS 8 is connected, at a node N6, to the drain of PMOS 6, and PMOS 5 turns on and off for outputting the potential level of the node N6 in response to the potential of the node N6.
FIG. 3 is a-waveform chart illustrating various operational waveforms of the level shifter circuit shown in FIG. 2. Now, description will be made as to an operation of the level shifter circuit shown in FIG. 2 with reference to FIG. 3.
When the potential level of the input signal .phi.1 changes from the potential Vss to the potential Vcc, the potential level of the node N4 becomes. Vcc by the two inverters 3 and 4, which causes NMOS 8 to turn on as shown in FIG. 3(a) so as to drop the potential of the output signal .phi.2. Concurrently, NMOS 7 turns to be off-state so that the potential of the node N5 turns to be the potential Vpp through PMOS 5 having on-state, in response to the potential of the output signal .phi.2. When the potential of the node N5 turns to be the potential Vpp, PMOS 6 turns to be off-state, which causes the level of the node N6 to be the ground level Vss so that the level of the output signal .phi.2 becomes the ground potential Vss.
Consequently, when the potential level of the input signal .phi.1 changes from the potential level Vcc to the potential level Vss, the inverter 3 changes the level of the node N3 from the ground potential level Vss to the potential level Vcc and turns NMOS 7 to be on-state. The inverter 4 changes the level of the node N4 to be the ground potential level Vss. As a result, NMOS 8 turns to be off-state, the level of the node N5 drops down from the potential level Vpp to the potential level Vss, and PMOS 6 and PMOS 5 respectively turn to be on and off states. Accordingly, the level of the node N6 becomes the potential level Vpp and the level of the output signal .phi.2 becomes the potential level Vpp.
As described above, when the potential level of the input signal .phi.1 changes from the potential level Vss to the potential level Vcc, the potential level of the output signal .phi.2 shifts from the level Vpp to the level Vss. On the other hand, when the potential level of the input signal .phi.1 changes from the level Vcc to the level Vss, the potential level of the output signal .phi.2 shifts from the level Vss to the level Vpp.
There is disclosed a conventional level shifter circuit similar to the aforementioned one shown in FIG. 2 applied to a DRAM word line driving circuit in, for example, an article entitled as "Circuit Techniques For a Wide Word I/O Oath 64 Meg DRAM" authored by K. Komatsuzaki et al. and published in a VLSI symposium 91.
FIG. 4 is a circuit diagram illustrating another conventional level shifter circuit, and FIG. 5 is a waveform chart illustrating operational waveforms of the circuit shown in FIG. 4. The circuit shown in FIG. 4 is constructed by supplementing a latch circuit 10 in the level shifter circuit shown in FIG. 2. As a result, the level shifter circuit shown in FIG. 4 can perform a level conversion operation similarly as the conventional circuit shown in FIG. 2 if a control signal .phi.c is being supplied. However, if the control signal .phi.c is not being supplied, the output signal maintains a constant level regardless of the level of the input signal.
The level shifter circuit employs the latch circuit 10 for holding a potential which connects therethrough respective drains of PMOS 5, PMOS 6, NMOS 7 and NMOS 8. The latch circuit 10 is constituted of two transistors NMOS 11 and NMOS 12, each gate and drain of which is mutually cross connected with each other between the drains of each PMOS 5 and PMOS 6, and each source of which is connected to the ground potential level Vss, and a switch circuit 13. The switch circuit 13 is constituted of NMOS 15 which connects PMOS 5 with NMOS 7 by applying the control signal .phi.c to its gate, and NMOS 16 which connects PMOS 6 with NMOS 8 by applying the control signal .phi.c to its gate.
The level shifter circuit shown in FIG. 4 can operate in the same manner as the level shifter circuit shown in FIG. 2, the operational waveforms of which is shown in FIG. 5, provided that the control signal .phi.c is being supplied, and can operate in such a manner that NMOS 15 and 16 turn to be off state if the control signal .phi.c is not provided. Accordingly, the potential level of the output signal .phi.2 is preserved regardless of the potential of the input signal .phi.1.
However, the conventional level shifter circuit encounters the following problems.
When the potential of the input signal .phi.1 changes from the potential Vcc to the potential Vss or from the potential Vss to the potential Vcc, a rush current flows from the second power source potential Vpp to the ground potential Vss.
There is another problem that a delay time is long which is defined as a period of time during when the potential of the output signal .phi.2 changes from the potential Vss to the potential Vpp after the potential of the input signal .phi.1 has changed from the potential Vcc to the potential Vss or during when the potential of the output .phi.2 changes from the potential Vpp to the potential Vss after the potential of the input signal .phi.1 has changed from the potential Vss to the potential Vcc. In other words, when the input signal .phi.1 changes, as shown in FIG. 3(a), from Vcc to Vss, the inverter 3 changes the potential of the node N3 from Vss to Vcc, thereby NMOS 7 turning to be on-state. However, since the output signal .phi.2 still stays in the potential Vss, both of PMOS 5 and NMOS 7 turn to be ON-state so that a large amount of rush current I1 flows and it also takes time that the potential of the node N5 turns to be the potential Vss. Further, when the potential of the node N5 drops, causing to turn PMOS 6 on, a large amount of rush current flows up until when the potential of the node N4 turns to be the potential Vss.
Next, when the potential of the input signal .phi.1 changes, as shown in FIG. 3(b), from the potential Vss to the potential Vcc, the potential of the node N4 changes, by the inverters 3 and 4, from the potential Vss to the potential Vcc. Accordingly, NMOS 8 turns to be ON-state, causing to turn both of PMOS 6 and NMOS 8 on, so that a large amount of rush current flows.
On the other hand, it is prevented that the potential of the output signal .phi.2 turns to be the potential Vss. Although no rush current flows in the level shifter circuit shown in FIG. 4 if the control signal .phi.c is not input because level shift has not occurred, the rush current flows in the same way, like the circuit shown in FIG. 2, if the level shift has been occurred by inputting the control signal .phi.c. There is also a problem that the delay time is long during when the potential of the output signal .phi.2 changes from the potential Vss to the potential Vpp after the potential of the input signal .phi.1 has changed from the potential Vcc to the potential Vss or during when the potential of the output .phi.2 changes from the potential Vpp to the potential Vss after the potential of the input signal .phi.1 has changed from the potential Vss to the potential Vcc.
As described above, the conventional technology has problems that the rush current has inevitably been generated and the delay time is long. In a semiconductor circuit, in particular, in which the second power source potential is generated internally, increase of the rush current imposes heavy burdens on the internal voltage elevation circuit, which has caused a problem to affect operations of the other circuits.